In coherent optical transmission, digital coherent receiver with digital signal processing (DSP) is the key enabling technology to realize polarization demultiplexing, demodulation and impairments compensation. In high speed optical transmission, DSP is implemented in hardware as application specific integrated circuit (ASIC) as programmable digital signal processor(s) cannot meet the processing speed requirement.
One of the limiting factors in ASIC development may be the long developing cycle covering the algorithm design, i.e. floating point simulation, fixed-point simulation, offline/real-time verification to chip design, chip silicon foundry, chip debugging, etc. Furthermore, every modification in the algorithm needs to run over the complete procedure round once more. This increases non-recurring engineering (NRE) costs and suffers from time-delay of new product releases. The disadvantage of current art is the inflexibility, i.e., for each update of the DSP algorithm, one has to design and tap-out the chip once more. This produces higher costs and time delay and makes the coherent receiver inflexible with respect to design variations.
Another approach using programmable FPGA has the limited capacity which could not support the data-throughput requirements in 100G coherent receiver applications. For example, the 112 Gbps OTN optical signal with 8 bits and 2 Sa/s will have 1.79 Tbps capacity to be processed. The FPGA devices provided by Xilinx and Altera have limited I/O capacity. Additionally the logical elements in the FPGA could not support the complicated functions. For example, one prototyping from NEC in 2010 ECOC Tu.5.A.2 used 16 cards with FPGAs which could not be used for prototyping nor could it be used for commercialization because of the large size and high cost.